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3D Integrated Circuit

DateFeb, 2007
Pages193
Price / format£2370 / PDF
£2370 / PRINT

£2 370 





Abstract:

Semiconductor chips face constant pressure for increased performances while still decreasing their size. At the same time their packages must be able to accommodate new functionalities. The ever-expanding consumer electronics market is a particularly strong driver of packaging innovations such as 3D ICs.

Today wire bonding is limited in density and performances so 3D stacking with micro-vias (or TSV, ""through-Si vias"") seems to be unavoidable in the future for miniaturization first and increased performances after.

3D integration will use technologies originally developed for MEMS technology but for different markets. In our report, we have analyzed that portable applications are a strong market driver for 3D integration.

Stacking memories, stacking memories and logic, image sensors with µP and FPGAs will be the first mass market applications. In 2010, we forecast that 1 billion of Flash memories will be stacked with TSVs (see figure 1).

3D-ICs: the technical challenges are close to be overcome

3D is the most ""integrated"" approach and is an enabling technology platform applicable to digital and mixed signal electronics, wireless, electro-optical, MEMS, sensors, smart imagers, displays and other devices. There are however strong challenges. They are: thermal management, reliable co-design and simulation tools, industrial wafer-to-wafer bonding tools, low-cost through-wafer via structures and via fill processes. In our report we have analyzed and compared the different technical solutions and figure 2 shows an example of process cost comparison for TSVs realization.

Why buy this report?

We are at the crossroads of numerous breakthroughs in 3D stacking! Although 3D ICs are at the R&D stage in the largest semiconductor companies today, the recent announcement of Samsung in 2006 could speed up micro-via technology especially for the memory business. By acquiring the new Yole 3D IC report, you will have access to:

  1. An overview of the different 3D packaging approaches (SoC, SiP ...)
  2. What are the market drivers and market forecasts for 3D ICs
  3. The status of development for the different identified players (ICs, image sensors)
  4. The evolution of the business models (OSAT, IDMs, wafer fabs ...)
  5. How the adoption of 3D stacking could significantly change the standard semiconductor process (FEOL vs. BEOL)
  6. The equipment and materials market forecasts for 3D integration (for DRIE, laser, bonders and materials)
  7. An analyze of the different technical solutions
    • Doing the TSVs (Through Silicon Vias) — electrically isolated interconnections through the silicon, which requires laser or deep reactive ion etching (DRIE) to create through vias.
    • Filling the TSVs with different materials (copper, tungsten, polySi, conductive polymers ...)
    • Thin wafers handling, usually below 50 µm.
    • Alignment and bonding of wafer-to-wafer or chip-to-wafer or chip-to-chip.
    • Bonding technologies by silicon fusion, polymer bonding, direct copper-to-copper, copper-tin eutectic bonding.

Who should buy this report?

This report targets both devices manufacturers and packaging companies as 3D will be such a breakthrough for packaging than developments are running whatever the activity of the semiconductor companies.
This report is of great interest for equipments manufacturers as well, as new investments are planned in a close future for implementing all the 3D technological steps.
So, whatever is your responsibility, R&D, production, marketing or business development, the Yole 3D IC report will give you a deep insight for markets and technological challenges for 3D integration.

List of interviewed companies for the report

3D-Plus, All-via, Amkor, ASE, ASM International, Dow Corning, E2V, EM Microelectronics, Fraunhofer IZM, Freescale, Fujikura, Fujitsu, Hymite, Hynix Semiconductor, IMEC, Infineon, Intel, Leti, Matsushita Electric Works, MEMSiC, Micron, MicroResist, NEC, Nokia, Philips Image Sensors, Philips Semiconductors, Samsung, Semitool, SensoNor, Silex, SPIL, STMicroelectronics, SÜSS microtec, Synova, Tessera, Texas Instruments, TSMC, VTI Technologies, VTT, Xintec, XSil, Ziptronix, Zycube


Table of contents:
  • List of figures
  • Acronyms & definitions
  • Objectives of the report
  • Advanced packaging challenges
    • Packaging evolution
    • From 2 D to 3D
    • Trends for stacking
    • SoC, SiP and 3D IC
    • 3D interconnect technology trend
  • 3D IC markets
    • Definition of TSVs
    • Market drivers
    • Memories
      • Memories segmentation
      • Where TSVs will be use
      • Flash memory market
      • Roadmap for 3D IC players
    • Image sensors
      • TSVs for image sensors
      • Roadmap
      • Examples
    • MEMS
  • Packaging supply chain
    • Supply chain of packaging players
    • Impact on business models
  • Equipment and materials market forecasts
    • Hypothesis
    • Market forecasts
  • 3D IC - Scenarios for stacking chips
    • Different approaches for going to 3D
    • 3D IC Interconnect technologies
    • Bonding processes
      • Overview of bonding technologies
      • Via-first vs. via-last
      • TSVs manufacturing
    • Cost comparison
    • DRIE vs. laser
    • Vias characteristics
    • Vias filling
    • TSVs vs. wire bonding
      • W2W versus C2W
      • Bonding cost comparison
  • Handling of thin die/wafers issues
  • Grinding/thinning concepts
  • Examples of 3D developments
  • Conclusions on 3D ICs
  • Annexes
    • Packaging definitions
    • Bonding cost comparison
    • List of interviewed companies
    • Yole Developpement presentation
    • Presentation of Yole's Multi-Customer Action





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